The present invention relates to phase-locked loops, and more particularly to a power conserving phase-locked loop such as may be used as a frequency synthesizer in wireless communications devices.
Phase-locked loops are used to perform a wide variety of tasks, such as frequency synthesis, AM and FM detection, frequency multiplication, tone decoding, pulse synchronization of signals from noisy sources, and regeneration of clean signals, particularly in wireless communications devices. Because batteries power many wireless communications devices that use a phase-locked loop, such as cellular telephones and the like, and because battery lifetime is a major concern for many consumers, new designs for phase-locked loops that reduce power consumption are obviously desirable.
Typically, phase-locked loops include an oscillator for generating the output signal and suitable comparing/locking circuitry. The comparing/locking circuitry outputs a control signal to the oscillator to control the frequency and phase output of the oscillator, thereby ensuring that the output signal is at the desired frequency and phase. The comparing/locking circuitry typically utilizes a bias current to help generate the control signal. In prior art phase-locked loops, the bias current is generated the entire time the phase-locked loop is in an active state (i.e., turned on) and therefore provides a constant drain on the batteries powering the device. While the bias current may be a small fraction of the final output current, it nevertheless represents a significant part of the total current consumption of the phase-locked loop. As such, a new design of phase-locked loop that helps reduce the power drain of the bias current supply would be desirable, particularly in helping to meet consumer demand for improved wireless communications devices with longer battery life.